In general, the present invention relates to a dynamic random-access memory, such as a DRAM. More particularly, the present invention relates to a semiconductor device having a configuration comprising a DRAM and other semiconductor elements, such as a logic circuit.
Miniaturization of a DRAM cell raises a problem in that it is difficult to assure that the capacitance of the capacitor for accumulating an electric charge will be large enough for cell operations due to the fact that the capacitance is reduced by the miniaturization. There have been proposed a variety of techniques to solve this problem. According to one of the techniques, a stack DRAM cell wherein an accumulation electrode is created typically over a word line.
In this memory cell, however, if a accumulator capacitor is created by utilizing the area of the plane portion, the capacitance of the capacitor is reduced as the memory cell is made smaller in size. For this reason, there have been proposed a variety of techniques for increasing the area of the physical shape of the capacitor in the thickness direction of the semiconductor substrate. Nevertheless, it is difficult to implement a DPAM having a capacity of at least 256 Mbit with any of the these techniques.
Concrete examples of the conventional technology are as follows. The capacitor structures shown in FIGS. 1 to 3/are referred to as an STC (Stacked Capacitor), a crown-STC and a FIN-STC, respectively. In each of the structures, one capacitor is provided for each cell. It should be noted that, in FIGS. 1 to 3 reference numeral 0 denotes a semiconductor substrate and reference numeral 1 denotes an insulation film for separating elements from each other. Reference numerals 2 and 3 denote a word line and a bit-line contact plug, respectively. Reference numeral 4 denotes an accumulation-node contact plug and reference numeral 5 denotes a bit line. Reference numerals 7 and 9 denote a capacitor insulation film and a lower electrode, respectively. Reference numeral 14 denotes a capacitor insulation film and reference numeral 15 denotes an upper electrode.
Japanese Patent Laid-open No. Hei 4-83375 discloses a Capacitor structure for high density DRAM cells wherein three fences are created on an area occupied by an accumulation electrode by using first and second protrusions.
In addition, Japanese Patent Laid-open No. Hei 4-212449 discloses an example wherein two capacitors are provided, being stretched over two memory cells in order to secure a large capacitance in the conventional capacitor structure, while assuring a high integration density. For these capacitors, which have a configuration stretched over two memory cells, the capacitors are extended in the direction of the bit line.
It is thus an object of the present invention to provide a semiconductor device which is capable of assuring a higher capacitance for a memory capacitor while securing a higher density of integration.
The present invention solves a variety problems that are inherent in the conventional technology. One problem involves the difficulty in securing a sufficient capacitance in a capacitor due to a limitation imposed by the fabrication technology to assure sufficient space between capacitors for a shrunk cell area accompanying high-scale integration and miniaturization. Another problem involves an unavoidably reduced yield, which inevitably results in a rising cost of manufacture caused by the fact that the structure of the capacitor is made complicated and the height of the capacitor is increased in order to obtain a sufficient capacitance of the capacitor.
In the case of the memory cell structure described above, as the miniaturization of the memory cell continues, the area occupied by the lower electrode of the capacitor can not help but be reduced. This is because a limitation on the miniaturization by the fabrication technology imposes a limit on the size of the area occupied by the lower electrode. To be more specific, in order to secure a space between capacitors, the cell area can not help reduced. Thus, in order to obtain a sufficient capacitance, the structure of the capacitor is made complicated and the height of the capacitor is increased. An increased number of manufacturing processes and finer processes inevitably lower the product yield and raise the cost of manufacture.
FIG. 4 is a diagram showing the structure of a capacitor disclosed in Japanese Patent Laid-open No. Hei 4-83375. FIG. 4 is a top-view layout of two sets each serving as a unit. One of the sets comprises a first protruding lower electrode 21 and a second protruding lower electrode 22. The other set comprises a first protruding lower electrode 23 and a second protruding lower electrode 24. Three fences are used as the electrode surfaces of the capacitor. The three fences are a fence between the first protruding lower electrode 21 and the second protruding lower electrode 22, a fence between the first protruding lower electrode 23 and the second protruding lower electrode 24 and a fence between the first protruding lower electrode 21 and the first protruding lower electrode 23. In this capacitor structure, however, the first protruding lower electrode 21 and the second protruding lower electrode 22 are created by using a self-matching technique, while the first protruding lower electrodes 23 and 24 are created among themselves by using lithography technology. Thus, as miniaturization progresses, problems are created, such as a decreased yield of-similar products and an increased cost.
A first aspect of the present invention relates particularly to the structure of a stack capacitor cell (STC) and its manufacturing method. That is, a lower electrode of a capacitor for a memory is designed to comprise two portions, namely, a bottom and a wall-shaped body and the lower electrode is mounted in such a way that the longitudinal direction of the wall-shaped body is oriented toward the upper portion of the semiconductor substrate in order to increase the area of the capacitor electrode. In addition, the wall-shaped body and an insulation layer for the capacitor are created by using a so-called self-matching technique, while each layer is created by using the CVD (Chemical Vapor Deposition) method. It is to be noted that the use of a plurality of wall-shaped bodies is just natural and desirable from the capacity-enhancement point of view.
The self-matching technique provided by the present invention is a method whereby, once the position of a protruding body for creating a first wall-shaped body of a capacitor has been determined, members of the capacitor, that is, a second wall-shaped body and the insulation layer, are implemented without a mask process. If the CVD method is used in the creation of these layers, the film thickness of each of the layers can be adjusted with a high degree of freedom. Accordingly, it is possible to create a capacitor structure having a higher capacitance at a density that can be set freely without regard to the area of the memory cell.
According to a second aspect of the present invention, capacitors are created at contiguous locations over a plurality of memory cells which are laid out in the direction of the word line of a semiconductor memory device. Tn such a contiguous arrangement of capacitors, a capacitor can be created in a space between cells which is not used in the conventional design. As a result, the capacitance of the capacitor can be further increased.
An implementation by a combination of these two aspects of the present invention makes it possible to secure a capacitor having a high capacitance for a memory while assuring a high-density integration. For example, it is possible to implement a semiconductor memory device having a storage capacity of at least 256 Mbit.
In addition, by creating a lower electrode of a capacitor by using a plurality of wall-shaped bodies and by adopting the self-matching technique to produce a wall-shaped body of smaller width and an insulation film of smaller thickness, an upper electrode of the capacitor can be created, which is stretched over a plurality of memory cells laid out in the direction of a word line on the upper side of the stacked-layer body. In the direction of a word line on the upper side of the stacked-layer body, it is easy to obtain a large area. This technique is thus beneficial to creation of a capacitor with a large area.
Next, an outline of various aspects of the present invention will be described.
In the following aspects (1) to (3) of the present invention, a capacitor is particularly created, which is stretched over a plurality of memory cells.
(1) According to a first aspect of the present invention, there is provided a semiconductor device including at least a word line, a bit line and a capacitor having a first electrode and a second electrode over a semiconductor substrate, wherein the capacitor is created over the word and bit lines, while stretched over a plurality of memory cells.
(2) According to a second aspect of the present invention, there is provided a semiconductor device including at least a word line, a bit line and a capacitor having a first electrode and a second electrode over a semiconductor substrate, wherein the capacitor is created over the word and bit lines over the semiconductor substrate, while being extended in the direction of the word line and stretched over a plurality of memory cells.
According to the second aspect of the present invention, the capacitor is extended in the direction of the word line and stretched over a plurality of memory cells to secure a larger area of occupation for the capacitor.
(3) According to a third aspect of the present invention, there is provided a semiconductor device comprising a MOS transistor created on a semiconductor substrate and a capacitor electrically connected to either a drain area or a source area of the MOS transistor wherein the capacitor is extended in the direction of a word line and stretched over a plurality of memory cells.
The semiconductor device according to the third aspect of the present invention is a semiconductor memory device.
Fourth to sixth aspects (4) to (6) of the present invention in particular relate to the structures of lower electrodes of a capacitor.
The fourth to sixth aspects of the present invention particularly relate to the first aspect of the present invention. Members of a capacitor according to the fourth to sixth aspects (4) to (6) of the present invention, such as an insulation film and a wall-shaped body of a first electrode, as well as members used in processes of manufacturing the capacitor members, are fabricated by using a CVD method so that the thickness and the spacing of each member can be adjusted. Thus, by adopting the so-called self-matching technique, at least, these members can be created to produce fine capacitor cells at a pitch equal to half a minimum fabrication dimension during the fabrication of the semiconductor device.
(4) According to the fourth aspect of the present invention, there is provided a semiconductor device comprising a MOS transistor created on a semiconductor substrate, word and bit lines over the semiconductor substrate and a capacitor which has a first electrode placed on a semiconductor-substrate side and which is electrically connected to either a drain area or a source area of the MOS transistor, and a second electrode placed on a side opposite to the semiconductor-substrate side, wherein:
the capacitor is created over the word and bit lines;
the first electrode of the capacitor has a bottom and a plurality of wall-shaped bodies electrically connected to the bottom; and
the second electrode of the capacitor is placed over the first electrode, being separated from the first electrode by an insulation film.
(5) According to the fifth aspect of the present invention, there is provided a semiconductor device comprising a MOS transistor created on a semiconductor substrate, word and bit lines over the semiconductor substrate and a capacitor which has a first electrode placed on a semiconductor-substrate side and which is electrically connected to either a drain area or a source area of the MOS transistor, and a second electrode placed on a side opposite to the semiconductor-substrate side, wherein:
the capacitor is created over the word and bit lines;
the first electrode of the capacitor has a bottom and a plurality of wall-shaped bodies electrically connected to the bottom;
the second electrode of the capacitor is placed over the first electrode, being separated from the first electrode by an insulation film; and
the capacitor is stretched over a plurality of memory cells.
According to the fifth aspect of the present invention, the capacitor is stretched over a plurality of memory cells so that an area occupied by the capacitor can be increased.
(6) According to the sixth aspect of the present invention, there is provided a semiconductor device comprising a MOS transistor created on a semiconductor substrate, word and bit lines over the semiconductor substrate and a capacitor which has a first electrode placed on a semiconductor-substrate side and which is electrically connected to either a drain area or a source area of the MOS transistor, and a second electrode placed on a side opposite to the semiconductor-substrate side, wherein:
the capacitor is created over the word and bit lines;
the first electrode of the capacitor has a bottom and a plurality of wall-shaped bodies electrically connected to the bottom;
the second electrode of the capacitor is placed over the first electrode, being separated from the first electrode by an insulation film; and
the capacitor is extended in a direction of the word line and stretched over a plurality of memory cells.
According to the sixth aspect of the present invention, the capacitor is extended in a direction of the word line and is stretched over a plurality of memory cells so that an area occupied by the capacitor can be further increased.
(7) According to a seventh aspect of the present invention, there is provided a semiconductor device comprising semiconductor device elements and a semiconductor memory element which are created over a semiconductor substrate wherein the semiconductor memory element is a storage element having the capacitor according to any one of the first to sixth aspects of the present invention and the semiconductor device elements each have a function different from that of the semiconductor memory element. Examples of the semiconductor device elements each having a function different from that of the semiconductor memory element are a logic circuit and a microcomputer. It is needless to say that the semiconductor memory element having the capacitor provided by the present invention can be combined with other semiconductor devices.
Eighth to tenth aspects (8) to (10) of the present invention relate to desirable conditions of a method of locating the capacitor and a method of forming the lower electrode.
(8) According to the eighth aspect of the present invention, there is provided a semiconductor device wherein a capacitor is stretched over 2n (the nth power of 2) memory cells laid out at a contiguous location where n is a natural number.
(9) According to the ninth aspect of the present invention, there is provided a semiconductor device wherein the relation x less than d less than (x+Y) holds true where the symbol d denotes a gap between bottoms of two adjacent capacitors, the symbol x denotes the thickness of the wall-shaped body and the symbol y denotes a gap between two adjacent wall-shaped bodies.
(10) According to the tenth aspect of the present invention, there is provided a semiconductor device as in any one of the fourth, fifth and sixth aspects of the present invention wherein the relation z=n (x+y) holds true where the symbol n is a natural number, the symbol z denotes the length of the capacitor cell in a direction, the symbol x denotes the thickness of the wall-shaped body and the symbol y denotes a gap between two adjacent wall-shaped bodies.
An eleventh aspect of the present invention relates to an embodiment implementing a semiconductor memory device using a memory mat.
(11) According to the eleventh aspect of the present invention, there is provided a semiconductor device including a memory mat having a plurality of units each comprising a plurality of memory cells and a capacitor stretched over the memory cells.
Twelfth to fourteenth aspects (12) to (14) of the present invention relate to connections of the capacitor to the semiconductor-substrate side and particularly to the MOS-transistor side. The twelfth to fourteenth aspects (12) to (14) of the present invention are described in general terms as follows.
In the first place, in a semiconductor device according to any one of the aspects of the present invention, a unit comprises a plurality of memory cells and a capacitor stretched over the memory cells and the contact position of each storage node of the capacitor in each unit is shifted in the direction of its respective bit line.
In the second place, in a semiconductor device according to any one of the aspects of the present invention, a unit comprises a plurality of memory cells and a capacitor stretched over the memory cells, the contact position of each storage node of the capacitor in each unit is shifted in the direction of its respective bit line and at least one of storage-node contacts is created right above a contact drawn from a source or drain area.
However, the storage-node contact may be created at a position other than a location right above a contact drawn from a source or drain area. To put it completely, in the third place, semiconductor device according to any one of the aspects in a of the present invention, a unit comprises a plurality of memory cells and a capacitor stretched over the memory cells, the contact position of each storage node of the capacitor in each unit is shifted in the direction of its respective bit line and at least one of the storage-node contacts is created at a position other than a location right above a contact drawn from a source or drain area.
Representative embodiments according to the aspects of the invention will be described briefly.
(12) According to the twelfth aspect of the present invention, there is provided a semiconductor device including a MOS transistor created on a semiconductor substrate and a capacitor electrically connected to either a source area or a drain area of the MOS transistor wherein:
the capacitor is connected to either the source area or the drain area of the MOS transistor through a conductive layer; and
a planar-coordinate position of a junction between the source area or the drain area of the MOS transistor and the conductive layer is different from a planar-coordinate position of a junction between the capacitor and the conductive layer.
(13) According to the thirteenth aspect of the present invention, there is provided a semiconductor device as in any one of the aspects (1), (2), (3), (5) and (6) of the present invention with the semiconductor device including a MOS transistor created on a semiconductor substrate and a capacitor electrically connected to either a source area or a drain area of the MOS transistor wherein:
the capacitor is connected to either the source area or the drain area of the MOS transistor through a conductive layer; and
a planar-coordinate position of a junction between the capacitor and the conductive layer is shifted in the direction of the bit line from a planar-coordinate position of a junction to the source area or the drain area of the MOS transistor and the conductive layer.
(14) According to the fourteenth aspect of the present invention, there is provided a semiconductor device including a MOS transistor created on a semiconductor substrate and a capacitor electrically connected to either a source area or a drain area of the MOS transistor wherein:
the capacitor is connected to either the source area or the drain area of the MOS transistor through a conductive layer; and
a planar-coordinate position of a junction between the source area or the drain area of the MOS transistor and the conductive layer virtually coincides with a planar-coordinate position of a junction between to the capacitor and the conductive layer.
Next, methods to fabricate the semiconductor devices provided by the present invention will be described briefly.
(15) According to a fifteenth aspect of the present invention, there is provided a method of fabricating a semiconductor device comprising the steps of:
carrying out a process to prepare a semiconductor substrate and to create at least a semiconductor element having source and drain areas of a MOS transistor on the semiconductor Substrate and a bit line, a bit-line contact and a storage-node contact on the semiconductor element;
carrying out a process to create a bottom surface of a first electrode of a capacitor of the semiconductor device by separation using an insulation layer; and
carrying out a process to provide gaps among a plurality of wall-shaped conductive layers connected to the bottom surface of the first electrode of the capacitor by creation and removal of predetermined layers using a CVD (Chemical Vapor Deposition) technique.
(16) According to a sixteenth aspect of the present invention, there is provided a method of fabricating a semiconductor device comprising at least the steps of:
(a) carrying out a process to prepare a semiconductor substrate and to create at least a semiconductor element having source and drain areas of a MOS transistor on the semiconductor substrate and a bit line, a bit-line contact and a storage-node contact over the semiconductor element;
(b) carrying out a process to create a bottom of a first electrode of a capacitor of the semiconductor device by separation using an insulation layer;
(c) carrying out a process to create a first insulation layer having a comb-tooth shape over the semiconductor substrate prepared in this way with the layer having a thickness large enough for inserting at least an insulation layer constituting a portion of a plurality of wall-shaped bodies of a capacitor and a conductive layer constituting a part of a plurality of wall-shaped bodies of the capacitor;
(d) carrying out a process to create a plurality of first wall-shaped body conductive layers of the capacitor and a plurality of second wall-shaped body conductive layers of the capacitor separated from each other by a predetermined gap with the position of the first insulation layer with a comb-tooth shape taken as a base;
(e) carrying out a process to create an insulation layer on the surfaces of the first wall-shaped body conductive layers, the second wall-shaped body conductive layers and the bottom of the first electrode of the capacitor created in this way; and
(f) carrying out a process to create a second electrode of the capacitor.
In the fabrication method described above, if the position of the first insulation layer with a comb-tooth shape is determined by using a photo mask, the other members of the capacitor can be created and fabricated by adoption of the so-called self-matching technique which does not use a photo mask.
(17) According to a seventeenth aspect of the present invention, there is provided a method of fabricating a semiconductor device as in the sixteenth aspect of the present invention wherein, at the step of carrying out a process to create a plurality of first wall-shaped body conductive layers of the capacitor and a plurality of second wall-shaped body conductive layers of the capacitor separated from each other by a predetermined gap, the layers are created by adopting a CVD technique.